公司名称：誉诚（深圳）实业科技有限公司

The PLL-based clock module provides four modes of operation:•INTOSC1 (Internal Zero-pin Oscillator 1): This is the on-chip internal oscillator 1. This can providethe clock for the Watchdog block, core and CPU-Timer 2•INTOSC2 (Internal Zero-pin Oscillator 2): This is the on-chip internal oscillator 2. This can providethe clock for the Watchdog block, core and CPU-Timer 2. Both INTOSC1 and INTOSC2 can beindependently chosen for the Watchdog block, core and CPU-Timer 2.•Crystal/Resonator Operation: The on-chip (crystal) oscillator enables the use of an externalcrystal/resonator attached to the device to provide the time base. The crystal/resonator is connected tothe X1/X2 pins. Some devices may not have the X1/X2 pins. See Table 2-5 for details.•External Clock Source Operation: If the on-chip (crystal) oscillator is not used, this mode allows it tobe bypassed. The device clocks are generated from an external clock source input on the XCLKIN pin.Note that the XCLKIN is multiplexed with GPIO19 or GPIO38 pin. The XCLKIN input can be selectedas GPIO19 or GPIO38 via the XCLKINSEL bit in XCLK register. The CLKCTL[XCLKINOFF] bitdisables this clock input (forced low). If the clock source is not used or the respective pins are used asGPIOs, the user should disable at boot time.Before changing clock sources, ensure that the target clock is present. If a clock is not present, then thatclock source must be disabled (using the CLKCTL register) before switching clock